完全基于机器学习、生产力10倍提升，全球EDA巨头Cadence推出全新芯片设计自动化工具Cerebrus

Global EDA giant Cadence has launched Cerebrus, a new chip design automation tool based entirely on machine learning to boost productivity by 10 times

电子设计自动化（EDA）是指利用计算机辅助设计（CAD）软件，完成超大规模集成电路（VLSI）芯片的功能设计、综合、验证、物理设计（包括布局、布线、版图、设计规则检查等）等流程的设计方式。

Electronic design automation (EDA) refers to the use of computer aided design (CAD) software, complete VLSI chip function design, integration, verification, physical design (including layout, wiring, layout, design rules check) and other processes of the design.

作为应用计算机 / 电子工程的一个重要领域，EDA 有着悠久的历史，并仍在积极融合前沿算法和技术。近年来，随着半导体技术的发展，集成电路（IC）的规模呈指数级增长，这对电路设计流程的可扩展性与可靠性提出了挑战。因此，EDA 算法和软件在处理低延时超大搜索空间的情况下需要更有效、更高效。EDA 更是被誉为「半导体产业上的明珠」，在半导体整个产业价值链中起到举足轻重的作用。

As an important field of applied computer/electronic engineering, EDA has a long history and is still actively incorporating cutting-edge algorithms and technologies. In recent years, with the development of semiconductor technology, the scale of integrated circuits (ics) has grown exponentially, which challenges the scalability and reliability of circuit design processes. Therefore, EDA algorithm and software need to be more effective and efficient in the case of low latency and large search space. EDA is known as the "pearl in the semiconductor industry" and plays a pivotal role in the value chain of the semiconductor industry

机器学习技术在 EDA 领域的应用可以追溯至上世纪 90 年代，并且近年来，基于机器学习的 EDA 逐渐成为热门话题，研究人员提出了许多利用机器学习改进 EDA 方法的研究。这些研究几乎涵盖了芯片设计流程的所有阶段，包括设计空间缩减与探索、逻辑综合、布局、布线、测试、验证、制造等。

The application of machine learning technology in EDA field can be traced back to the 1990s. In recent years, EDA based on machine learning has gradually become a hot topic. Researchers have put forward many researches on improving EDA methods by using machine learning. These studies cover almost all stages of the chip design process, including design space reduction and exploration, logic synthesis, layout, wiring, testing, validation, manufacturing, etc.

最近，全球 EDA 三大巨头之一的 Cadence 推出了首款基于全机器学习的设计工具 Cerebrus，可以实现数字芯片设计的自动化与规模化。Cadence 数字与签核事业部产品工程资深群总监刘淼表示：「芯片设计中自动化的机器学习流程优化可以助力设计工程师在消费电子、移动设计、汽车、5G 通讯和超大规模计算登新型应用领域快速开发芯片。」

Recently, Cadence, one of the three major EDA companies in the world, launched Cerebrus, the first design tool based on full machine learning, which can realize the automation and scale of digital chip design."Automated machine learning process optimization in chip design can help design engineers rapidly develop chips for new applications in consumer electronics, mobile design, automotive, 5G communications and ultra-large scale computing," said Liu Miao, senior group Director of product engineering at Cadence's Digital and Signature Business Division.."

总的来说，Cerebrus 具有以下特性：

In general, Cerebrus has the following characteristics:

首先，引领了生产力和性能、功耗与面积（PPA）的创新革命。采用独一无二的增强型机器学习，实现了高达 10 倍的工程生产力提升，20% 的 PPA 结果改进。

Overall, Cerebrus has the following characteristics: First, it has led the innovation revolution in productivity and performance, power consumption and area (PPA). Using unique enhanced machine learning, we achieved up to 10-fold increase in engineering productivity and 20% improvement in PPA results.

其次，实现了 RTL-to-GDS 的全流程自动优化，从而能够更迅速地提供更佳的 PPA，提升设计团队的工作效率和生产力。

Secondly, the whole process of RTL-to-GDS is automatically optimized, which can provide better PPA more quickly and improve the efficiency and productivity of the design team.

最后，采用了可扩展、分布式计算解决方案。利用本地或云端的计算资源，这种高效可扩展的解决方案可以应对设计规模和复杂度的不断攀升。

Finally, scalable, distributed computing solutions were adopted. Using computing resources on site or in the cloud, this efficient and scalable solution can cope with the increasing scale and complexity of the design.

Cerebrus 如何实现生产力提升

How does Cerebrus achieve productivity gains

在设计过程中，Cerebrus 和 Cadence RTL-to-signoff 流程强强联合，为高阶工艺芯片设计师、CAD 团队和 IP 开发者提供支持，与手动开发流程相比，开发速度提升了 10 倍，同时 PPA 结果改善了 20%。

During the design process, the Cerebrus and Cadence RTL-to-signoff processes work together to support higher-order process chip designers, CAD teams, and IP developers, delivering a 10-fold increase in development speed and a 20% improvement in PPA results compared to manual development processes.

Cadence 以 5nm 制程手机 CPU 的设计为例，说明了 Cerebrus 相较于手动设计流程的巨大优势。对于 5nm、3.5GHz 的 CPU 设计，采用手动开发，多名工程师需要耗费数月时间。使用 Cerebrus 之后，1 名工程师仅在 10 天内，即可显著改善流程推动设计收敛。

Cadence used the design of a 5nm mobile phone CPU as an example to illustrate Cerebrus's great advantages over the manual design process. For a 5nm, 3.5GHz CPU design, it took several months of manual development by multiple engineers. With Cerebrus, one engineer was able to significantly improve the process and drive design convergence in just 10 days.

相较于基线，Cerebrus 将产品性能提升了 14%，漏电功耗降低了 7%，总功耗降低了 3%，密度提升了 5%。这就是全机器学习赋能的自动化芯片设计流程的优势所在。

Compared to the baseline, Cerebrus improved product performance by 14%, reduced leakage power by 7%, reduced total power by 3%, and increased density by 5%. This is where a fully machine learning-enabled automated chip design process comes in handy.

在另一个 12nm、2GHz 的 CPU 核心设计案例中，Cadence 展示了机器学习在自动布局规划优化中的作用。Cerebrus 可以同时优化布局规划与实现流程，在总失效时序与漏洞功耗方面均实现了显著提升，从而实现了客户要求在 CPU 上达到 2GHz 速率的目标。

In another example of a 12nm, 2GHz CPU core design, Cadence demonstrates the role of machine learning in automatic layout planning optimization. Cerebrus can simultaneously optimize layout planning and implementation processes, achieving significant improvements in both total failure timing and vulnerability power consumption, thus achieving the customer's goal of achieving a 2GHz CPU rate

最后，从更大的发展视角来看，Cerebrus 是 Cadence 数字全流程的一部分，可与 Genus 综合解决方案、Innovus 设计实现系统、Tempus 时序签核解决方案、Joules RTL Power Solution、Voltus IC Power Integrity SolutionIC 电源完整性解决方案以及 Pegasus Verification System 各个工具平台无缝集成合作，为客户提供快速的设计收敛和更好的可预见性。

And finally, from a larger perspective, Cerebrus is part of Cadence's digital process, It can be used with Genus comprehensive Solution, Innovus design implementation system, Tempus timing signature solution, Joules RTL Power Solution, Voltus IC Power Integrity SolutionIC Power integrity solutions and Pegasus Verification System tool platforms seamlessly integrate to provide customers with rapid design convergence and better predictability.

Cerebrus 也得到了瑞萨电子（Renesas）、三星晶圆厂（Samsung Foundry）等合作客户的广泛认可。

Cerebrus is also widely recognized by partner customers such as Renesas and Samsung Foundry.

关于 Cadence

Cadence

Cadence 在计算软件领域拥有超过 30 年的专业经验，是电子设计产业的关键领导者。基于公司的智能系统设计战略，Cadence 致力于提供软件、硬件和 IP 产品，助力电子设计概念成为现实。Cadence 的客户遍布全球，皆为最具创新能力的企业，他们向消费电子、超大规模计算、5G 通讯、汽车、移动、航空、工业和医疗等最具活力的应用市场交付从芯片、电路板到系统的卓越电子产品。

Cadence has more than 30 years of professional experience in computing software and is a key leader in the electronic design industry. Based on the company's Intelligent Systems design strategy, Cadence is committed to providing software, hardware and IP products that help make electronic design concepts a reality. Cadence's customers around the world are the most innovative companies delivering superior electronics products from chips, circuit boards and systems to the most dynamic application markets in consumer electronics, hyperscale computing, 5G communications, automotive, mobile, aviation, industrial and medical applications.

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